1. Field of the Invention
The present invention relates to integrated circuit structures and, in particular, to multilevel metal interconnect structures for use in integrated circuits and methods for their manufacture.
2. Description of the Related Art
Typical integrated circuits (ICs) include multilevel metal interconnect structures that serve a variety of purposes, including carrying electrical signals between individual device elements in the IC, as well as providing power and a connection to ground and to external apparatus. FIG. 1 illustrates a typical multilevel metal interconnect structure 10 that includes patterned metal layers 12, 14, 16 and 18. Multilevel metal interconnect structure 10 is disposed above semiconductor substrate 20 and also includes interconnect dielectric material 22, a plurality of vias (e.g. via 24, via 26, and via 28); and contacts (e.g. contact 30, contact 32, and contact 34).
The patterned metal layers are made up of individual metal lines, such as metal lines 14A and 14B of patterned metal layer 14, carrying signals and providing power, etc.
Interconnect dielectric material 22 provides electrical isolation between the patterned metal layers (for example between patterned metal layers 12 and 14), as well as between metal lines within a given patterned metal layer (for example, between metal lines 14A and 14B of patterned metal layer 14). Although the conventional interconnect dielectric material is silicon dioxide (SiO.sub.2), others can also be employed (see U.S. Pat. No. 5,548,159 to Jeng, which is hereby fully incorporated by reference). Interconnect dielectric material 22 is typically formed by depositing a layer of dielectric material after the formation of a patterned metal layer, and stacking one after the other. Therefore, interconnect dielectric material 22 can include contiguous regions where those regions sharing a boundary are fabricated of different dielectric materials (for example, silicon dioxide and silicon nitride). For the sake of clarity, however, the "interconnect dielectric material" will be referred to in the singular throughout this specification, even though it is understood that it may in actuality include more than one dielectric material.
The vias of multilevel metal interconnect structure 10 provide electrical connections between the patterned metal layers separated by the interconnect dielectric material in a manner known in the art. Likewise, the contacts provide an electrical connection between the bottommost patterned metal layer (i.e. patterned metal layer 18) and semiconductor substrate 20.
As is understood by those skilled in the art, semiconductor substrate 20 can include a variety of device elements (not shown in the Figures) on its surface, such as conventional complementary metal oxide semiconductor (CMOS) and bipolar transistors, diodes and other devices.
A drawback of conventional multilevel metal interconnect structures is that their use in sub-micron ICs results in interconnect structure related resistance (R) and capacitance (C) that dominate and increase signal delay. This signal delay is due to the presence of the interconnect dielectric material completely surrounding the patterned metal layers. The presence of interconnect dielectric material in such a configuration creates a metal/dielectric/metal structure that is the source of several capacitance components during IC device operation. As illustrated in FIG. 2, these capacitance components include C.sub.a (i.e. line-to-line capacitance between neighboring metal lines of the same patterned metal layer); C.sub.b (i.e. interlayer capacitance between a metal line of one patterned metal layer and an immediately underlying metal line of another patterned metal layer) and C.sub.c (i.e. interlayer cross-coupling capacitance between a metal line of one patterned metal layer and a diagonally offset underlying metal line of an underlying patterned metal layer). The presence of these capacitances greatly limits device speed by increasing signal delay.
U.S. Pat. No. 5,449,953 to Nathanson et al. describes single level "airbridge" connecting structures for interconnecting monolithic microwave ICs. The manufacturing of these highly specialized structures is, however, not compatible with standard CMOS or bipolar semiconductor device interconnect processing and these structures do not provide a supporting layer beneath the "airbridge."
Still needed in the art is a low capacitance multilevel metal interconnect structure that is simple to manufacture, compatible with standard CMOS and bipolar semiconductor device manufacturing, and provides for increased IC device speed.